1. Field of the Invention
This invention relates to FET semiconductor devices and more particularly to capacitor structures formed on FET semiconductor devices.
2. Description of Related Art
U.S. Pat. No. 5,045,899 of Arimoto for xe2x80x9cDynamic Random Access Memory Having Stacked Capacitor Structurexe2x80x9d shows a DRAM in which a plurality of word-lines (WL) and a plurality of bit-lines are arranged to orthogonally intersect each other. Memory cells are arranged in a direction intersecting the bit-lines. Capacitors of the memory cells are arranged between the adjacent bit-lines. On a silicon substrate, the bit-line is formed substantially at the same height with the word-line and positioned lower than the top of the capacitor. The arrangement of the capacitors between the adjacent bit-lines allows reduction in the inter-bit-line capacitance.
U.S. Pat. No. 5,107,459 of Chu et al. for xe2x80x9cStacked Bit-Line Architecture for High Density Cross-Point Memory Cell Arrayxe2x80x9d shows a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other.
U.S. Pat. No. 5,449,934 of Shono et al. for xe2x80x9cSemiconductor Memory Device and Processxe2x80x9d shows a DRAM memory device with a COB (Capacitor Over Bit-line) structure with a Bitline below Capacitor arrangement. The storage capacitor contact passes through a bit-line, a drain and source can be arranged symmetrically with a word-line, like a memory cell with a bit-line below-storage-capacitor organization cell.
FIGS. 3A and 3B provide a comparison of prior art COB (FIG. 3A), and CUB (FIG. 3B) designs for DRAM cells.
The COB design of FIG. 3A shows the bit-lines BLA below the capacitor C1 with a high degree of coupling capacity CCA. The CUB design of FIG. 3B shows the bit-lines BLB above the capacitor C1 with a high degree of coupling capacity CCB, roughly equivalent to coupling capacity CCA.
The process flow for the COB design for 8F2 DRAM cells of Kohyama et al. is described as follows:
An article by Kohyama et al., xe2x80x9cA Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyondxe2x80x9d, 1997 Symposium on VLSI Technology Digest of Technical papers Paper 3A-1, pp. 17-18 (1997) describes an 0.18 micrometer DRAM technology and beyond, the cell on folded-bit-line architecture has minimum cell of 8F2.
FIGS. 1A-1C show the first part of a prior art process flow of the Kohyama et al. with a plan view and cross-sectional layouts of the process flow, from isolation to self-aligned polysilicon (Poly) plug formation.
For simple patterns, F represents the minimum feature by a unit square of Fxc3x97F dimensions, where F is the minimum feature size limited by lithography. There are several key techniques must met in order to achieve an 8F2 cell. 1. The mask pattern must be simple to get a larger range of focus depth. 2. Self-aligned node contact to the bit-line must be realized. 3. Planarization by CMP (Chemical Mechanical Polishing) is used extensively.
Kohyama et al. suggests a fabrication method for a COB 8F2 DRAM cell with all three of the above listed features as shown in FIGS. 1A and 1B.
1. STI Isolation
The first part of the prior art process is described with reference to FIGS. 1A-1C for cell area, with the process starting with the well-known Shallow Trench Isolation (STI) process as shown in silicon oxide regions STI surrounding active regions AA in the silicon semiconductor substrate of device 10 which is a fragment of a semiconductor wafer. The depth of the trenches is approximately 0.2 xcexcm. Illustrations of the process in the periphery area are not shown.
2. Well Formation
Next follows formation of an N-well in the periphery which is not shown and a P-well 11 in the silicon semiconductor substrate of device 10. The process employed uses well known process steps for implantation of phosphorus and boron respectively in a selective process.
3. Transistor Gate Formation
Gate Oxide/Gate Stack (e.g. polysilicon/WSi2/Si3N4 deposit)
Then a gate oxide layer GX with a thickness of about 60 xc3x85 (not to scale in FIG. 1B) is grown on the surface of P-well 11. with gate oxide layer GX grown above isolation regions STI. Then polycide gate stack material layers of a first polysilicon layer 14, tungsten silicide (WSi2) layer 16 and first silicon nitride (Si3N4) dielectric layer 18 are deposited.
Gate Stack Mask/Etch (Word Lines (WL) and transistors)
Then a set of transistor gate electrode stacks for word lines in an array and transistors in the periphery are defined by masking and etching to form transistor gate electrode stacks (as shown Word Lines WL1, WL2, WL3 and WL4 in FIGS. 1A and 1B and the layers 14, 16 and 18 shown in FIG. 1B). SiO2/Si3N4 Deposition (Deposit spacer layers)
Next, spacer layers including a blanket layer of silicon oxide spacer layer SP and a blanket second silicon nitride (Si3N4) spacer layer are deposited.
Peripheral Area N+, P+, S/D Mask/Implant, RTA Anneal
A mask is used to open the peripheral area. Then the second Si3N4 spacer layer is etched to form spacers SP for the transistors in the periphery area. Please notice that the silicon nitirde (Si3N4) spacer layer remains on the cell at this stage of the process.
Transistor LDD regions and source/drain regions, etc. (not shown because they are in the periphery area and are well known process steps) are defined and formed by implanting NLDD, N+, PLDD, and P+ regions selectively followed by a RTA (Rapid Thermal Anneal) annealing step for removing defects resulting from implantation steps.
BPSG Deposition, CMP
Next a BPSG glass layer BG1 is deposited followed by a thermal reflow for the BPSG layer BG1. Next follows a CMP (Chemical Mechanical Polishing) step of planarizing the BPSG glass layer BG1 surface. The CMP step will stop on the top of the second nitride (spacer) layer in the cell area.
4. Self-aligned Polysilicon plug formation SAC Mask/Etch (Stop on Silicon Nitride)
Next, plug holes through layer BG1 are prepared for formation of a lower set of self-aligned polysilicon plugs PL1 which are to be formed later. The plug holes are made by using a SAC (Self-Aligned Contact) mask, which is the same as the active area (AA) mask, but shifted one F as shown in FIG. 1A and described by Kohyama et al. (above), and etching the BPSG layer BG1 on those open areas of the SAC mask with a wet etchant. This wet etching step stops at the second Si3N4 (spacer) layer. Notice that the SAC mask is the same as the AA mask but is shifted by one F, and the entire periphery area is protected.
Cell Silicon Nitride Spacer Etch (Stop on Oxide)
Then, the second Si3N4 (spacer) layer is etched to form spacers for the cells by stopping on the silicon oxide spacer layer SP. Then the SAC contact mask photoresist is removed and the wafer 10 is cleaned.
NLDD Ion Implant
Next there is a blank NLDD ion implant for the cell node junctions shown as NLDD regions in FIGS. 1B and 1C.
Deposition of Doped Polysilicon and Polysilicon CMP
Then after a wet dip of the silicon oxide, a blanket N-type doped second polysilicon (plug) layer PL1 covering device 10 is deposited filling the plug holes formed in the SAC Mask/Etch above. Then the doped second polysilicon layer is polished by CMP which stops at the first silicon nitride layer 18 to finish formation of plugs PL1. The polysilicon plugs PL1 are now in contact with the silicon 11 beneath them and plugs PL1 serve the function as an extension (electrically) of the silicon substrate at the node contacts and the bit-line contacts.
Deposition of First IPO layer
Next a blanket first Inter-Polysilicon, silicon Oxide (IPO) dielectric layer IP1 is deposited over device 10. As seen in the cross-section in FIG. 1B, layer IP1 covers the plugs PL1, and the first Silicon Nitride (Si3N4) layer 18. As seen in the cross-section in FIG. 1C, first inter-polysilicon, silicon oxide dielectric IP1 covers the plugs PL1 and the BPSG layer BG1.
FIGS. 2A-2C show the second part of a prior art process flow of Kohyama et al. with a plan view and cross-sectional views of the results including bit-line formation, self-aligned node capacitor formation, and the back-end process.
5. Bit-line (Damascene W) Formation
A set of bit-lines BLA are formed in openings in the first inter-polysilicon, silicon oxide dielectric layer IP1 by a well known damascene W (tungsten) process with Si3N4 spacer and capping. This initiates the second stage of the process producing results shown in FIGS. 2A-2C.
Bitline Trough Mask/Etch
First, bit-line trough masking and plasma etching of silicon oxide with an end point at the polysilicon is performed to form bit-line openings in dielectric layer IP1 including openings for bit-line contacts to the polysilicon plugs PL1.
Deposit Silicon Nitride and Etch Back
Then a third blank Si3N4, layer is deposited and etched back to form second spacers SP2 in the sidewalls of the bit-line openings.
Deposit Tungsten, CMP and Tungsten Etchback
Then the bit-lines BLA are formed in the bitline troughs by depositing a layer of tungsten (W) which is then planarized by a CMP process. A tungsten (W) etchback step follows leaving a gap between the surface of the device 10 and the tungsten bit-lines BLA which are recessed slightly below the surface of the first inter-polysilicon, silicon oxide dielectric layer IP1. Bit-lines BLA rest in the bitline troughs upon the surface of the remainder of dielectric layer IP1.
Silicon Nitride Deposition and CMP to Cap Bit Lines
Next a fourth Si3N4 layer is deposited and planarized by a CMP process providing caps 20 over the bit-lines BLA as seen in FIG. 2C.
6. Cross-point node contact formation
Then, a self-aligned capacitor node is formed by a technique referred to as xe2x80x9ccross-point node contactxe2x80x9d in Kohyama et al. formed as a node at the cross-point at the cross-point of the Word Line (WL) mask opening line and the Si3N4 caps 20 over W bit-lines BLA.
Node Contact Mask/Etch Silicon Oxide
First the node contact mask (which is the same as the WL mask with the periphery area protected) is formed and contact node contact openings are formed by plasma etching down into the first inter-polysilicon, silicon oxide dielectric layer IP1. The etching of the node contact openings stops on the first Si3N4 layer 18 and the polysilicon node, i.e. plug PL1 and the Si3N4 caps 20.
Form Silicon Nitride Liner (Deposition and Etchback)
Next Si3N4 liners 22 are formed by deposition of a Si3N4 layer which is etched-back leaving liners on the walls of the node contact openings.
Deposit Doped Polysilicon Followed by CMP (CMP of Poly)
Then the node is filled with polysilicon doped with phosphorus formed into storage plugs PL2 by the pattern of the node contact openings. Then the top surfaces of storage plugs PL2 are planarized by a CMP process stopped on Si3N4 caps 20. The plugs PL2 are in contact polysilicon plug PL1 and the substrate 11 now.
Deposit Second IPO Layer
A second inter-polysilicon, silicon oxide dielectric (IPO) layer IP2 is formed covering device 10. Silicon oxide layer IP2 covers polysilicon storage plugs PL2, first inter-polysilicon, silicon oxide dielectric (IPO) layer IP1 and silicon nitride caps 20.
7. Concave capacitor formation
Storage Cavity Mask/Etch (Stop on Si3N4)
Then a capacitor cavity is defined by a mask followed by etching silicon oxide inter-polysilicon, silicon oxide dielectric IP2 stopping on the Si3N4. layer (caps 20) and exposing the surface of the storage plugs PL2.
Deposit Lower Capacitor Electrode Plate Layer and CMP (e.g. Ru, or polysilicon)
Then, referring to FIGS. 2B and 2C, above the storage plugs PL2, very thin lower capacitor electrode plates are formed in electrical and mechanical contact with the upper surfaces of storage plugs PL2. The lower electrode plates are composed of a conductor, e.g. a doped polysilicon conductor for a Ta2O5 dielectric or a Ru (Ruthenium) conductor for a BST (Barium Strontium Titanate) dielectric respectively for the capacitor. The lower conductor materials are deposited and planarized by CMP.
Deposit Dielectric and Plate (e.g. BST/Ru, or Ta2O5/TiN/Poly)
Next, the capacitor dielectric material layer 24 (e.g. Ta2O5 or BST) is deposited over the lower capacitor electrode plates (above plugs PL2).
Top Plate Mask/Etching
The top capacitor plate material (e.g.Ru or TiN/doped polysilicon for BST or Ta2O5 respectively) is then deposited and patterned by a mask to form the top plate TP. Thus the capacitors are formed above the upper plugs PL2 and above the top surfaces of the bit-lines BLA.
8. Back-end: ILD, CMP, Periphery Contacts C3, M2, Via, M3, Fuse, Passivation, Polyimide
The fabrication is completed by conventional back-end process steps (e.g. contact, M2, IMD, Via, M3, fusing, passivation, polyimide). Note that the bit-line is considered to be metal 1 (M1).
There is a similar process flow for 8F2 CUB DRAM cell in the Capacitor Under Bit-line (CUB) is also considered to be possible from the flow in Kohyama et al. by modifying the process sequence. The capacitor material can also be either Ta2O5 or BST. Notice that the capacitor capacitance values are limited by area constraints. Thus the foot prints are the same for either COB or CUB designs, i.e. 3F2 in FIG. 2A since the capacitor cannot be extended above or below the bit-line area but can be extended over the word-line due to the minimum feature size F.
Problems which require improvement are as follows:
1. The above-described process flow requires high aspect ratio contacts in the periphery area. The COB design requires contact in the periphery area with a high aspect ratio. The CUB design requires bit-line contact with a high aspect ratio.
2. The bit-line to bit-line coupling is a serious problem.
3. The COB or CUB design cannot increase the footprint of the capacitor since under 8F2 cell layout, the capacitor can be extended only over the word-line area (i.e. in the X-direction in FIGS. 2A-2C) but not in the bit-line area and the footprint is 3F2.
The invention shows a CEB design - capacitor on the same level as the bit-line.
In accordance one aspect of this invention, a device with bit lines and a capacitor for a semiconductor memory device includes a gate oxide layer on a doped silicon semiconductor substrate. Gate electrode/word-line stacks are juxtaposed with doped polysilicon plugs over the gate oxide layer. The doped polysilicon plugs are separated by a first dielectric material in a direction transverse to the gate electrode/word-line stacks. A first interpolysilicon layer overlies the doped polysilicon plugs. There are bit-lines in the first interpolysilicon layer above the first dielectric material and capacitors above the plugs, between bit-lines.
Preferably, the capacitor comprises a thin conductive layer of doped polysilicon on the surface of the polysilicon plugs having been polished by CMP, a capacitor dielectric layer composed of Ta2O5/TiN above the thin conductive layer, and an upper plate of the capacitor composed of doped polysilicon above the capacitor dielectric layer.
Preferably, a dielectric layer overlies the bit-lines of a silicon nitride layer to seal the bit-lines. A second interpolysilicon layer is formed above the bit-lines. The second interpolysilicon layer has been planarized by chemical mechanical polishing.
Preferably, the gate electrode stacks comprise gate electrode/word-line stacks and the gate electrode stacks comprise doped polysilicon plugs.